Turbo decoder architecture for use in software-defined radio systems
US7571369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2005 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Jul 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2978
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reconfigurable turbo decoder comprising N processing units. Each of the N processing units receives soft input data samples and decodes the received soft input data samples. The N processing units operate independently such that a first processing unit may be selected to decode the received soft input data samples while a second processing unit may be disabled. The number of processing units selected to decode the soft input data samples is determined by a data rate of the received soft input data samples. The reconfigurable turbo decoder also comprises N input data memories that store the received soft input data samples and N extrinsic information memories that store extrinsic information generated by the N processing units. Each of the N processing units is capable of reading from and writing to each of the N input data memories and each of the N extrinsic information memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.