Wafer level package having a stress relief spacer and manufacturing method thereof
US7572673B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2006 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Feb 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01087
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.