Thyristor-based semiconductor memory device with back-gate bias
US7573077B1 · kind B1 · utility
15Cited by
16References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 4, 2005 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Nov 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B99/22
Abstract
In accordance with an embodiment of the present invention, a thyristor-based semiconductor memory device may comprise an array of thyristor-based memory formed in an SOI wafer. A supporting substrate may be formed with a density of dopants sufficient to assist delivery of a bias level to the backside of an insulating layer beneath a thyristor. Such conductivity within the substrate may allow reliable back-gate control for the gain of a component bipolar device of the thyristor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.