Semiconductor wafer examination method and semiconductor chip manufacturing method
US7573256B2 · kind B2 · utility
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11References
29Claims
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Key dates
| Filing date | Jul 10, 2007 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Jul 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2881
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor wafer examination method that includes: preparing a wafer formed with a chip area for use as a semiconductor chip; firstly examining the wafer by probing; pressing an electrode of the wafer with a pressure member having a flat surface; and secondly examining the wafer by probing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.