Programmable logic based latches and shift registers
US7573293B2 · kind B2 · utility
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76References
20Claims
0Family size
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Key dates
| Filing date | May 12, 2008 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | May 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch is described, comprising: a first programmable logic element (LE); and a second programmable logic element (LE); and an output of the first LE adapted to directly couple to a first input of the second LE; and an output of the second LE coupled to a first input of the first LE; and a first common input coupled to a second input of the first and second LE; and a second common input coupled to a third input of the first and second LE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.