Programmable logic based latches and shift registers
US7573294B2 · kind B2 · utility
1Cited by
77References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2008 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | May 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a programmable logic device adapted to implement a shift register, the device comprising: a logic block comprised of: a latch having an input; and a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element. In the device, the logic element is configured as a route through for the latch output to couple to the adjacent logic block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.