High speed divider circuit
US7573305B1 · kind B1 · utility
5Cited by
1References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2008 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Mar 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/542
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed divider circuit is disclosed. The circuit contains a plurality of latches and buffers. The maximum input clock frequency of the divider circuit is increased over that implemented with only latches connected in a ring by feed forwarding the output of an early switching latch to the output of a later switching latch through buffers. The feed forward signal aids the later switching latch to complete the next state transition. By choosing the appropriate ratio of the buffer tail current to the latch tail current, the divider circuit can be made into a dynamic divider circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.