Logic level voltage translator
US7573313B2 · kind B2 · utility
3Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2005 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Aug 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/102
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage level translator provides an output signal having an external voltage in response to an input signal having an internal voltage. The voltage level translator includes first and second input signal transistors, first and second output signal transistors, and includes a signal stabilization circuit and/or an enable circuit. A ready-signal generation circuit provides a ready signal indicating that a voltage supply is at an operating voltage. The ready-signal generation circuit can include unbalanced transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.