Apparatus and methods for adjusting performance of integrated circuits
US7573317B2 · kind B2 · utility
13Cited by
6References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2006 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Sep 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.