High efficiency digital power amplifier
US7573330B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Oct 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital power amplifier (or power switching amplifier or power switch) for use in a digital transmitter includes a low impedance multi-stage driver circuit having a low impedance pre-driver and a low impedance driver. The drive circuit drives a power switch stage having two power transistors configured in a current mode class-D push-pull configuration. Utilization of gallium nitride (GaN) transistors or pseudomorphic high electronic mobility transistors (pHEMT) (or combination thereof) and sizing the transistors progressively larger in the driver than in the pre-driver (at least about 3×) provides a reduction in output impedance of the driver circuit and progressive increases in the power driving capability of the succeeding stage. This allows the use of a power amplifier at higher frequencies without altering or affecting the power efficiency and allows use of a digital power amplifier for a digital transmitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.