Patent · US Active

Setting threshold voltages of cells in a memory block to reduce leakage in the memory block

US7573775B2 · kind B2 · utility

12Cited by

3References

14Claims

0Family size

Assignee

FUJITSU LIMITED · JP

Inventors

Farzan Fallah · San Jose, US
Behnam Amelifard · Los Angeles, US
Massoud Pedram · Beverly Hills, US

Key dates

Filing date	Feb 9, 2007
Grant date	Aug 11, 2009
Priority date	—
Expiry date	Apr 8, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/22
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one or more of the bit lines has a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.