Input threshold adjustment in a synchronous data sampling circuit
US7573967B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2005 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Feb 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data sampler system receives a high-speed data stream and uses a first set of data samplers for sampling the data stream at a first set of clock phase angles to produce a first set of sequential data “eye” samples. A second set of data samplers, to sampled at a second set of clock phase angles that are different from the first set of clock phase angles to produce a second set of sequential data transition samples. The first set of data samplers, the data stream is sampled at the second set of clock phase angles to produce a third set of sequential data transition samples and with the second set data samplers, the data stream is sampled at a first set of clock phase angles to produce a fourth set of sequential data “eye” samples. The system alternates between the first mode and a second mode in which the results produce a reduced input offset voltage for the sampler system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.