Counter using shift for enhanced endurance
US7573969B2 · kind B2 · utility
5Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2007 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Feb 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A counting device includes a set of memory cells, which are configured to store respective bits of a count code. A controller is coupled to the memory cells so as to increment, in response to occurrences of a count input, the count code in the set of the memory cells from an initial value up to a preset bound in each of a plurality of successive iterations, and to shift the bits of the count code that are respectively stored in the memory cells in each of the iterations relative to a preceding iteration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.