Method and apparatus for generating a phase-locked output signal
US7574185B2 · kind B2 · utility
7Cited by
11References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Jan 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for generating a phase-locked output signal includes generating an intermediate signal phase locked to an input signal by frequency dividing the intermediate signal by a temporally-varying divide ratio sequence to generate a first feedback signal and phase comparing the first feedback signal with the input signal. An output signal is generated phase locked to the first feedback signal by frequency dividing the output signal by the temporally-varying divide ratio sequence to generate a second feedback signal and phase comparing the second feedback signal with the first feedback signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.