Processor array including delay elements associated with primary bus nodes
US7574582B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 26, 2004 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Jan 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a processor array, which achieves an approximately constant latency. Communications to and from the farthest array elements are suitably pipelined for the distance, while communications to and from closer array elements are deliberately “over-pipelined” such that the latency to all end-point elements is the same number of clock cycles. The processor array has a plurality of primary buses, each connected to a primary bus driver, and each having a respective plurality of primary bus nodes thereon; respective pluralities of secondary buses, connected to said primary bus nodes; a plurality of processor elements, each connected to one of the secondary buses; and delay elements associated with the primary bus nodes, for delaying communications with processor elements connected to different ones of the secondary buses by different amounts, in order to achieve a degree of synchronization between operation of said processor elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.