Memory device having a power down exit register
US7574616B2 · kind B2 · utility
10Cited by
89References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2004 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Jan 22, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.