Method and system to optimize timing margin in a system in package module
US7574687B1 · kind B1 · utility
0Cited by
3References
5Claims
0Family size
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Key dates
| Filing date | Jan 3, 2006 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Oct 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10689
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a System-in-Package (SiP) module, a method and a system for optimizing the timing margin of source-synchronous interface clocks is provided. Clock signals generated by first device are transmitted to serpentine traces located on a Printed Circuit Board (PCB) which adjusts the active edge of one signal relative to another signal. The serpentine trace introduces a delay in the clock signal thereby optimizing timing margins. By providing access to signals otherwise internal the SiP, testing and signal verification is also simplified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.