Semiconductor integrated circuit device and a manufacturing method for the same
US7575967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2006 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | May 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
Abstract
In a manufacturing method for a semiconductor device, a first impurity diffusion layer for a low impurity concentration drain of a second conductivity type is formed within a semiconductor layer of a first conductivity type, and a second impurity diffusion layer for a high impurity concentration drain of the second conductivity type is formed adjacent to the first impurity diffusion layer, with the second impurity diffusion layer having a higher impurity concentration than the first impurity diffusion layer. An interlayer insulating film is formed on the semiconductor substrate layer. A drain extension region having a high thermal conductivity is formed on a surface of the first impurity diffusion layer. A contact hole is formed through the interlayer insulating film and up to the second impurity diffusion layer. A wiring metal layer is then deposited into the contact hole to form therein a drain electrode that is electrically connected to the second impurity diffusion layer and that is disposed apart from and not in contact with the drain extension region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.