Semiconductor device and metal line fabrication method of the same
US7575998B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Jun 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.