Semiconductor integrated circuit for reducing leak current through MOS transistors
US7576405B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2006 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Feb 20, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is composed of: a power control region within which function cells are arranged; a basic power supply line overlapping said power control region, and positioned in a power supply interconnection layer; a virtual power supply line arranged in said power control region in a direction perpendicular to said basic power supply line, said function cells being connected to said virtual power supply line; a ground line arranged in said power control region in said direction perpendicular to said basic power supply line; a switch cell including a metal interconnection positioned in a metal interconnection layer different from said power supply interconnection layer, and a switch element electrically connected between said metal interconnection and said virtual power supply line; and a via contact connected between said basic power supply line and said metal interconnection. The switch cell is positioned within power control region. The switch element is positioned adjacent to said via contact within said switch cell. The metal interconnection is positioned between said virtual power supply line and said ground line within said switch cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.