Conducting layer in chip package module
US7576425B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 25, 2007 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Jan 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A conducting layer in a chip package module includes one or a plurality of through hole penetrating the top of a base being disposed at the bottom of an insulating layer in the chip package module, and inner wall of the through hole being applied with insulation material so that the conductive layer subsequently constructed to the peripheral of the insulation layer may pass the through hole to extend to where above the base before construction of a masking layer and multiple circuit pins to complete construction of the conducting layer that is totally enveloped so to prevent easy oxidization at the conducting layer and improve stability of the chip package to avoid breaking up due to external force applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.