Signal amplitude detection circuitry without pattern dependencies for high-speed serial links
US7576570B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2006 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Nov 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.