Patent · US Active

Switchable PLL circuit

US7576576B2 · kind B2 · utility

15Cited by

6References

12Claims

0Family size

Assignee

Thomson Licensing · FR

Inventors

Michael Drexler · Gehrden, DE
Ralf Schaefer · Cesson-Sévigné, FR

Key dates

Filing date	Nov 7, 2006
Grant date	Aug 18, 2009
Priority date	—
Expiry date	Nov 7, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/22
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An electronic circuit includes a first and a second PLL stage (PLL1, PLL2) that can be switched in parallel or in series depending on locking of the first one of the PLL circuits to an input signal (IN). When in parallel, only the second PLL circuit (PLL2) is actively supplying a clock signal to the output of the electronic circuit. The first PLL circuit (PLL1) continues trying to lock onto the input signal (IN). A lock detector (LD) monitors the locking status of the first PLL circuit (PLL1) to the input signal (IN) and, upon locking, sets switches (S1, S2) to couple the output of the first PLL circuit (PLL1) to the input of the second PLL circuit (PLL2), and to couple the output of the second PLL circuit (PLL2) to the input of the first PLL circuit (PLL1).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.