Analog-to-digital converter using lookahead pipelined architecture and open-loop residue amplifiers
US7576676B2 · kind B2 · utility
11Cited by
12References
35Claims
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Key dates
| Filing date | Oct 20, 2006 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Oct 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.