Memory storage technique for a bi-directionally programmable memory device
US7577028B2 · kind B2 · utility
5Cited by
0References
18Claims
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Inventor
Key dates
| Filing date | Mar 23, 2007 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Oct 29, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array with a programming region to store data. The programming region includes a plurality of memory cells and has an associated flag bit. Logic is coupled to the memory array. The logic is to compare data stored in the programming region to a desired programmed value, and to determine a number of changing bits. The logic may further set or clear the associated flag bit, depending on the number of changing bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.