Method and circuit for performing read operation in a NAND flash memory
US7577033B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Sep 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method and semiconductor circuit for providing a read operation in a NAND flash memory. The NAND flash memory includes an array of bit lines. The method includes selecting a first set of bit lines of the array of bit lines for performing the read operation. The first set of bit lines are pre-charged to a pre-defined voltage level. At the same time, a second set of bit line are also charged to the pre-defined voltage. The second set of bit lines are in anti-phase to the first set of bit lines. Further, reading of the first set of bit-lines is performed. The second set of bit lines is maintained at the pre-defined voltage level during the reading of the first set of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.