Source centered clock supporting quad 10 GBPS serial interface
US7577171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2003 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Nov 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.