Adaptive equalizer
US7577193B2 · kind B2 · utility
8Cited by
6References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2005 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Feb 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03477
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the invention include apparatus, systems, and methods to adjust a clock generator and an equalizer to reduce jitter in an output signal. A phase detector provides feedback information on a first feedback loop and a second feedback loop. A clock adjustment circuit uses the feedback information on the first feedback loop to adjust a clock generator. An equalizer adjustment circuit uses the feedback information on the second feedback loop to adjust the equalizer. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.