Reducing phase offsets in a phase detector
US7577224B2 · kind B2 · utility
2Cited by
16References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 28, 2004 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Oct 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D13/004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a system having an amplifier to receive an incoming signal and a recovery circuit coupled to the amplifier that includes a phase detector to adjust a phase of a sampling clock via a signal indicative of a difference between transitions occurring between the sampling clock and each of a first error clock and a second error clock. Based on a phase adjusted output of the phase detector, the sampling clock may be generated with an appropriate phase. Thus, circuitry and methods are provided to reduce or eliminate phase offsets in the phase detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.