Systems and methods for mitigating latency associated with error detection and correction
US7577890B2 · kind B2 · utility
0Cited by
15References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2005 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Jan 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for mitigating latency associated with error detection and correction of a data structure are disclosed. One embodiment of a system may comprise a packet generator that builds a response packet associated with a request for a data structure based on a tag portion of the data structure. The system may also comprise an error detection and correction (EDC) component that detects and corrects errors in the data structure concurrently with the building of the response packet by the packet generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.