Patent · US Active

Method and apparatus for extending decoding time in an iterative decoder using input codeword pipelining

US7577891B2 · kind B2 · utility

8Cited by
6References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 26, 2006
Grant dateAug 18, 2009
Priority date
Expiry dateApr 12, 2027

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03M13/2975
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receive a first codeword from the input buffer and process the first codeword. The iterative decoder processes the first codeword only for an amount of time required for the first codeword to become substantially error free. The decoder architecture further includes logic coupled to each of the iterative decoder and the input buffer. The logic is configured to determine when the first codeword processed by the decoder becomes substantially error free. The logic further generates a signal for loading a second codeword from the input buffer into the iterative decoder responsive to the logic determining when the first codeword becomes substantially error free.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.