Method and apparatus for analyzing integrated circuit operations
US7577930B2 · kind B2 · utility
2Cited by
142References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2005 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | Mar 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318544
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for viewing and/or analyzing the operations and logical states of an integrated circuit. The logical state of various flip-flops within the ASIC may be determined at a specified time. The embodiment may store these flip-flop states in a computer-readable data structure, such as a file or database. By repeating this process and incrementing or decrementing the time with each repetition, a more complete picture of the ASIC's operation may be captured. Additionally, the embodiment may graphically display the flip-flop states, for example as a graph or waveform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.