Timing driven pin assignment
US7577933B1 · kind B1 · utility
13Cited by
19References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2006 |
| Grant date | Aug 18, 2009 |
| Priority date | — |
| Expiry date | May 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design information includes a floorplan that sets forth an arrangement of blocks in the integrated circuit and timing information for interconnections between the blocks. Based on the timing information, routing information is determined for the interconnections between the blocks. The routing information includes physical routes and physical pin placements for the interconnections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.