Integrated circuit wafer packaging system and method
US7578392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2004 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Apr 9, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S206/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging system, hereinafter referred to as the Critical Packaging System, relates to critical issues that associate with sensitive articles such as IC wafers before, during and after shipment phases. The system employs a choice of two or more specialty designed containers, and any one selected design having choices of two or more methods by which to avoid, reduce and/or eliminate wafer damage from breakage, scratches and/or corrosion during shipment phases. For the purpose of maximizing product yield during packaging phases a special apparatus is used to insert wafers within containers without scratch damage. The following programs are used in packaging: (1) Quality Assurance/Certification, (2) Critical Factor Monitoring, and (3) a Recycle and Refurbish Program. These programs are specifically designed to achieve new levels of product yields, reduce product cost, and landfill impact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.