Memory interface optimized for stacked configurations
US7579683B1 · kind B1 · utility
56Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2004 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Jul 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so that the circuit layout of the semiconductor die is invariable with respect to the size of the memory die within a given range of sizes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.