Slew rate control circuit for small computer system interface (SCSI) differential driver
US7579873B1 · kind B1 · utility
3Cited by
80References
25Claims
0Family size
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Key dates
| Filing date | Nov 16, 2007 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Dec 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interface driver circuit comprises N cascaded delay cells, each including a data bit input, a delayed data bit output that communicates with the data bit input of an adjacent one of the N cascaded delay cells, and a delay time input that sets delay values between receiving data at the data bit input and generating the delayed data bit output. N predrivers receive an output enable signal that is independent of the data, receive a corresponding one of the N delayed data bit outputs and generate a predriver output signal based on the output enable signal and the corresponding one of the N delayed data bit outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.