Patent · US Active

DAC architecture for an ADC pipeline

US7579975B2 · kind B2 · utility

1Cited by

2References

3Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Sandeep Mallya Perdoor · Bengaluru, IN
Abhaya Kumar · Bengaluru, IN
Shakti Shankar Rath · Bengaluru, IN

Key dates

Filing date	Dec 11, 2007
Grant date	Aug 25, 2009
Priority date	—
Expiry date	Dec 11, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03M1/361
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.