Protecting circuits from electrostatic discharge
US7580233B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2005 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Jan 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/819
Abstract
Circuits and methods for protecting a circuit from an electrostatic discharge (ESD) event are disclosed herein. One such method includes detecting when a circuit to be protected is powering up and disabling an output driver of the circuit to be protected when the circuit is powering up. The power up sequence, for example, may be the result of a sensed ESD event. In addition, the present disclosure includes a circuit that comprises an ESD sensing circuit and a disable circuit. The ESD sensing circuit includes an RC circuit connected between VDD and VSS and a first inverter connected between a second inverter and a node that connects a resistor with a capacitor of the RC circuit. The disable circuit includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor configured to receive an EN signal from the second inverter, and the first NMOS transistor configured to receive an EN signal from the first inverter. The first PMOS transistor is further configured to connect a second PMOS transistor to VDD when EN is low, and the first NMOS transistor is further configured to connect a second NMOS transistor to VSS when EN is high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.