Semiconductor memory device comprising two rows of pads
US7580294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2007 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Aug 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first row of pads including a first plurality of data input/output (I/O) pads; a second row of pads including a second plurality of data I/O pads; and a first I/O multiplexer associated with the first row of pads and providing first output data only to at least one data I/O pad of the first row of pads, even after a data I/O mode of the semiconductor memory device has changed. The semiconductor memory device also includes a second I/O multiplexer associated with the second row of pads and providing second output data only to at least one data I/O pad of the second row of pads, even after the data I/O mode has changed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.