Memory device having open bit line structure and method of sensing data therefrom
US7580314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2007 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Nov 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory blocks. Each memory block includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells provided at intersections of the bit lines and word lines; a plurality of capacitors, and a plurality of sense amplifiers. Each sense amplifier has a first input and a second input. The first input is connected to a first bit line of a first one of the memory blocks and is coupled via one of the capacitors to a first bit line of a second one of the memory blocks. The second input of the input is connected to a second bit line of the second one of the memory blocks and is coupled via one of the capacitors to a second bit line of the first one of the memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.