Clock recovery
US7580492B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2005 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Dec 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Clock recovery apparatus having an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein the early/late voter passes and Up/Down signal to an interpolator for maintaining a clock signal; a frequency accumulator and rate multiplier 30 for generating further signals which are summed with those of the Up/Down signal of the early/late voter to provide an improved control signal to the phase interpolator. The accumulator is responsive to frequency changes in the input signal, and the interpolator acts on said Up/Down signals to adjust the clock signal by stepping it forward or backward according to control need, so that the sampling point can be advanced or retarded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.