Patent · US Active

Clock data recovery loop with separate proportional path

US7580497B2 · kind B2 · utility

30Cited by

5References

9Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Shoujun Wang · Gatineau, CA
Haitao Mei · Ottawa, CA
Bill Bereza · Ottawa, CA
Tad Kwasniewski · Ottawa, CA

Key dates

Filing date	Jun 29, 2005
Grant date	Aug 25, 2009
Priority date	—
Expiry date	May 26, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/033
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop filter, and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump and loop filter with stable second-order behavior, with the resistor R of the loop filter serving as a proportional path. A separate proportional path is also provided that provides phase detector output directly to a control input of the VCO, while the resistor R of the loop filter is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path may be activated to maintain second-order behavior.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.