Method of design analysis of existing integrated circuits
US7580557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2008 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Aug 29, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.