I/O hub resident cache line monitor and device register update
US7581042B2 · kind B2 · utility
2Cited by
4References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Sep 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a microprocessor. The cache monitor also associates cache lines in the microprocessor with I/O device registers. When an access to certain cache lines are detected, the cache monitor is operable to receive the contents of the cache line and write those contents to an associated I/O device register. Therefore, a microprocessor may write to a cache line, instead of making an uncacheable write to the I/O device register directly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.