System for a memory device having a power down mode and method
US7581121B2 · kind B2 · utility
73Cited by
89References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 14, 2005 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Mar 6, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.