Peripheral component interconnect bus test system and method therefor
US7581143B2 · kind B2 · utility
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Key dates
| Filing date | Feb 21, 2007 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Apr 26, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral component interconnect (PCI) bus test system and method therefor, that is applied in a PCI test card. The PCI test card includes a static random-access-memory (SRAM). In the method, the data transaction of the PCI bus signal is disintegrated into a separate data operation, while eliminating the waveform interfering transaction. Through comparing the waveform of the data operation as separated from a PCI bus signal with the standard PCI bus waveform, the quality of the PCI bus signals can be precisely analyzed, thus realizing the hardware test of PCI bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.