Method and apparatus to lower operating voltages for memory arrays using error correcting codes
US7581154B2 · kind B2 · utility
7Cited by
15References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Jun 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data from before and after the memory, correcting errors when the comparator determines a difference in the results of the error correction codes and lowering the operating voltage of the memory array while using the error correction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.