Use of state nodes for efficient simulation of large digital circuits at the transistor level
US7581199B1 · kind B1 · utility
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2Claims
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Key dates
| Filing date | Aug 8, 2005 |
| Grant date | Aug 25, 2009 |
| Priority date | — |
| Expiry date | Sep 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and the resulting output values and delays have been evaluated, another instance of the same module need not be re-simulated when it has the same input combination as the prior circuit module instance. The results computed earlier for the earlier circuit module instance can be re-used for the current circuit module instance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.