Delay lock clock synthesizer and method thereof
US7583117B2 · kind B2 · utility
6Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2006 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Oct 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay lock clock synthesizer comprises: an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset controlled by a control signal; a phase detector for detecting a phase difference between the input clock and the output clock and for generating a phase error signal representing the phase difference; a summing circuit for summing the phase error signal and a phase offset signal into a modified phase error signal; and a filter for filtering the modified phase error signal to generate the control signal to control the adjustable delay circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.