High-speed flip-flop circuit
US7583123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2005 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Feb 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop circuit that captures an input signal in sync with a clock, has a first gate outputting a first signal corresponding with input signal; a second gate generating a second signal of a first predetermined level in response to a first level of clock and causing the second signal to be a level of first signal in response to a second level of clock; and a third gate outputting a third signal of second signal in response to the second level of clock. Further the flip-flop circuit has a first inversion feedback circuit between the third and second signal terminals, that is activated in response to the second level of clock and latches the third signal together with third gate; and level fixing circuit that fixes the first signal terminal at a second predetermined level with a time delay after the clock changes to the second level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.